1. Field of the Invention
The present invention generally relates to a wireless reception wake-up system, and more particularly, to a wake-up receiver and wake-up method for minimizing power consumed by a radio frequency (RF) transceiver of a sensor node in a ubiquitous sensor network (USN).
The present invention is derived from a research project partly supported by the Information Technology (IT) Research & Development (R&D) program of the Ministry of Information and Communication (MIC) and the Institute for Information Technology Advancement (IITA) of Korea [2005-S-106-03, Development of Sensor Tag and Sensor Node Technologies for RFID/USN].
2. Description of the Related Art
As wireless communication become more widely used, networks integrating wired and wireless technologies have been deployed in various fields. Accordingly, requirements for a technical standard for high-speed, low-cost, and low-power wireless communications have been proposed.
To this end, various wake-up receivers have been introduced, which reduce power consumption and extend battery life by switching off a main transceiver in most cases and switching on the main transceiver only when it performs communications.
FIGS. 1 and 2 are circuit diagrams of conventional wake-up receivers.
Referring to FIG. 1, the conventional wake-up receiver includes a film bulk acoustic resonator (FBAR) amplifier 100, an envelope detector 110, a programmable gain amplifier (PGA) 120, an analog-to-digital converter (ADC) 130, and a band gap reference (BGR) device (140). The conventional wake-up receiver illustrated in FIG. 1 delivers a radio frequency (RF) signal to the envelope detector 110 by performing high impedance conversion by using the FBAR amplifier 100 and amplification of the RF signal by using a low noise amplifier (LNA) (not shown) in order to obtain a high reception sensitivity. However, the conventional wake-up receiver of FIG. 1 consumes much power due to the use of amplifiers and provides low reception sensitivity at remote sites. Moreover, due to the use of a special element, i.e., the FBAR amplifier 100, the conventional wake-up receiver is difficult to implement as a system-on-a-chip.
Referring to FIG. 2, the conventional wake-up receiver is constructed in 2 stages. A first stage of the two stages includes a detector 200, a comparator 210 and a timer 220, and a residual second stage includes an LNA 230, a detector 240, and an address decoder 250. In an operation of the conventional wake-up receiver of FIG. 2, when sensing a strong burst signal delivered from a transmission side, the conventional wake-up receiver sequentially operates the detector 200, the comparator 210, and the timer 220 in the first stage so as to supply power to the second stage, and switches the second stage to a data signal receiving mode, wherein the signal is received via the LNA 230. Once the first stage switches the second stage to a mode for data reception, the second stage receives data. Although the wake-up receiver illustrated in FIG. 2 consumes a small amount of power because the first stage, which is composed of the detector 200, the comparator 210, and the timer 220, uses no amplifier, it has a low reception sensitivity with respect to the strong burst signal and increases a chip area due to the use of 2 or more detectors. Moreover, the detector 200 in the first stage is a special element including a multi-stage zero-bias Schottky diode, and thus is difficult to integrate by using a complementary metal oxide semiconductor (CMOS) process.